1. Field of the Invention
The present invention relates to read only memory (ROM) devices and, in particular, to a ROM array that incorporates alternate metal virtual ground (AMG) memory array architectural concepts to provide ultra-high-density read only data storage.
2. Discussion of the Prior Art
U.S. Pat. No. 5,151,375 issued to Boaz Eitan on Sep.29, 1992 for EPROM VIRTUAL GROUND ARRAY, discloses an alternate metal virtual ground (AMG) EPROM array. The basic idea of the Eitan disclosure is the use of a "cross-point" EPROM cell, i.e. a cell that is defined by the perpendicular crossing of a polyl floating gate island and a poly2 word line in an array in which metal contacts alternate buried N+ bit lines. The contacted bit lines define the drain lines of the array, while the intermediate noncontacted bit lines define the source lines of the array. The source bit lines connect to ground via access transistors. Each drain bit line is contacted only once every 64 cells, the 64 cells connected to the same drain bit line constituting one "segment."
Turning now from AMG EPROM array concepts to ROM array concepts, which are the subject of the present invention, Okada et al., "16Mb ROM Design Using Bank Select Architecture", 1988 Symposium on VLSI Circuits; Digest of Technical Papers, 1988, p. 85-6, disclose a high density mask ROM array based on a bank selection architecture. Referring to FIG. 1, each ROM cell bank "n" in the Okada et al. array consists of sixteen word lines (WL0-WL15). The buried bit lines 2 in each bank are connected to aluminum lines 4 via bank select transistors 6. The alternating main bit lines M and virtual ground bit lines V are utilized in pairs to read data from the ROM storage cells 8.
As further shown in FIG. 1, the Okeda et al. ROM uses two types of bank select transistors. One type is used for reading ROM cells in "even" columns of the array. The other type is used for reading "odd" columns.
Referring to FIG. 2, when a selected ROM cell in an even column is accessed (e.g. the circled cell in FIG. 2), the selected word line WL0 and the bank select line SE.sub.n for the even columns both go high; the bank select line SO.sub.n for the odd columns goes low. As a result, the drain and source regions of the selected ROM cell are connected to the main bit line M and to the virtual ground line V, respectively. At the same time, the sources and drains of the ROM cells in the odd columns are shorted via the even columns bank select transistors which are activated by the even columns bank select line SE.sub.n.
Cells in odd columns are similarly accessed in accordance with the bias conditions shown in FIG. 3.
Referring back to FIG. 1, the alternating main bit lines M and virtual ground lines V run zigzag in the column direction of the array, alternately connecting the shorted nodes in the even and odd columns in adjacent ROM cell banks. Thus, the pitch of the aluminum lines 4 can be twice that of the buried N+ bit lines 2. This reduces both the capacitance and the possibility of shorts between the aluminum lines 4. It also allows cell size to be determined by the minimum pitch of the bit lines 2 rather than by the pitch of the aluminum lines 4.